Why does capacitive coupling require a base resistor in an emitter follower?

Images from Art of Electronics 1st edition, p. 58 (Horowitz and Hill)

Both of these circuits accept an AC signal that is centered around 0V.

The first (Figure 2.16) is supposedly coming from a previous amplifier stage where the output voltage is conveniently situated between the positive and negative voltage supplies.  The second (Figure 2.17) has been capacitively coupled and so (I presume) it is also sitting around 0V and fluctuating into both positive and negative territory.  The only difference between the two as nearly as my novice eyes can see is that one is coupled and one is not.  Horowitz and Hill state:

Warning: You must always provide a DC path for base bias current, even if it goes only to ground.  In the preceding circuit it is assumed that the signal source has a DC path to ground.  If not (e.g., if the signal is capacitively coupled), you must provide a resistor to ground. (Art of Electronics 1st Ed, p. 58)

I don't understand why both circuits don't need this resistor, and why the capacitor makes it necessary.

Capacitor in series needs a charge path but a discharge path also. The Rb ensures both part of this condition.

Without Rb the capacitor is charged through base only during positive cycle. But nothing allows to discharge the cap back during negative cycle. So the cap becomes fully charged after few periods and no signal passing.

In the first picture (2.16), no source is shown so the DC level is unknown, but as you refer to,

In the preceding circuit it is assumed that the signal source has a DC path to ground.

some kind of DC path is existing.

In figure 2.17, where a capacitor is explicitly shown, some kind of DC bias path is required. It could have been a standard voltage divider between Vcc and Vee with the base connected inbetween.

The capacitor prohibits the flow of DC current so if it is necessary to establish a DC operating point, some kind of DC bias path is required. In this case a single resistor is used. If no base current is flowing no collector current will flow. Base current would only flow in the beginning unttil the capacitor is charged up.

Here are CircuitLab simulations of the two circuits. I will add my explanations later.

Vin = 0 V



simulate this circuit – Schematic created using CircuitLab

Vin = 1 V AC



simulate this circuit



Vin = 0 V



simulate this circuit

Vin = 1 V AC



simulate this circuit



Ignore the emitter follower for a moment, and focus only on the capacitor and some source of input signal:



simulate this circuit – Schematic created using CircuitLab

Ask yourself what is potential \$V_B\$ at node B? The answer depends on what initial charge the capacitor has. If C1 starts completely discharged, with no potential difference between A and B, then the answer is:

$$ V_B = V_A + 0V = V_A $$

\$V_B\$ follows \$V_A\$. If \$V_A\$ rises by 1mV, then so will \$V_B\$, and if \$V_A\$ falls by 1mV \$V_B\$ will also fall by 1mV. There's no offset between A and B, so the capacitor is pointless here. You could achieve this behaviour by directly connecting B to A.

The utility of the capacitor is evident when the average DC potentials at A and B are different, creating a potential "gap" that needs bridging. Let's say that \$V_A=+5V\$ average, and \$V_B=+7V\$ average, then you have a gap of 2V to bridge. Charge the capacitor to 2V (more positive at its right end), so now the equation becomes:

$$ V_B = V_A + 2V $$

You still have \$V_B\$ following \$V_A\$ as it changes, but offset by 2V.

The purpose of the capacitor is to "bridge the DC voltage gap" between potentials \$V_A\$ and \$V_B\$ at nodes A and B, while permitting any change in potential \$\Delta V_A\$ to appear at B as an equal change \$\Delta V_B\$. This is called "AC coupling", or you could think of it as "DC blocking", if you like.

It works because A and B can have different average DC potentials, which the capacitor "bridges" by developing a long-term average DC charge and voltage according to \$Q=CV\$, but crucially any changes in potential at A are "copied" to B.

However, you must somehow get the capacitor to charge to 2V (or whatever is the average DC potential difference) in the first place. Clearly this is not possible above, because current \$I_1=0\$. There's no path to permit the DC current necessary to charge the capacitor to any DC potential difference other than zero.

We must somehow coerce the potential at B to whatever long-term value we desire, usually by using a resistance to that very potential:



simulate this circuit

Here we have a sinusoidal AC input at A provided by V2, centered at an average of +5V DC provided by V1. We want the average potential at B to be +7V DC, which we set by providing a path for DC current via R1 to a source of +7V, thanks to V3.

Start by assuming that there's no AC signal, the amplitude of V2 is zero. Also, the capacitor starts discharged. In this state, there is a DC potential difference of \$7V-5V=2V\$ across R1, causing current \$I_1\$ to flow, which will slowly charge C1. In this DC context, this is a simple RC arrangement in which the capacitor voltage rises exponentially to 2V (orange), and DC current (blue) eventually diminishes to zero:



Any fluctuations at A will still be copied to B, though, and eventually you find that fluctuations at B are centered 2V higher than those at A, because the capacitor's DC voltage eventually reaches a steady 2V:



This behaviour depends on a path existing for DC charging current through the capacitor, a path provided by R1, to a biasing potential V3. Without DC current through C1 to initially charge it, you have no idea what that initial charge is, and you can't predict the "center" average DC potential at B. For this reason, you never see the arrangement on the left below; rather, you'll find some variation on the arrangement to the right:



simulate this circuit

Op-amp input resistance is infinite, or at worst, very very large, and bias current \$I_{BIAS}\$ is zero, or poorly defined. Consequently, without R1 and some biasing potential, the average DC value of \$V_B\$ is unknown, entirely dependent upon the ambiguous state of charge of C1.

In the context of your question, the thing connected to B is not an op-amp, but an emitter follower. Without DC biasing (left) and with DC biasing (right), it looks like this:



simulate this circuit

The voltmeters show DC (quiescent) potential at the transistors' bases. On the left, without biasing, clearly DC quiescent base current has charged the capacitor with -11.5V of DC charge. Consequently, Q1's base is near the negative supply potential, and its output (emitter) will be stuck near -12V. Ideally we would like the output to be nearer to 0V, the middle of the -12V to +12V range. This is achieved on the right by biasing base potential using R2 to 0V.

Here are the outputs, emitter potential \$V_{E1}\$ (blue, no biasing) and emitter potential \$V_{E2}\$ (orange, biased near ground):



In your question you called \$R_B\$ (R2 here) a "base resistor". Using that name is misleading, because "base resistor" typically describes a resistor in series with the base, whose role is to limit base current in a common-emitter scenario:



simulate this circuit

The current-limiting role of R9 is very different from the biasing role of R2 in the prior circuits. \$R_B\$ and \$R_2\$ should be called "biasing" resistors, not "base" resistors. R9 here may be called a "base resistor".